Field of the Invention
The present invention relates to a method of compensating a phase of a system clock synchronous with an external clock in an information processing system and an apparatus employing the same, and more particularly to a method of compensating a phase of a system clock when a phase of an external clock is varied, an apparatus employing the same and a system clock generator.
In order to synchronize an information system, e.g., a local area network (hereinafter, referred to as "LAN" for short, when applicable) with a digital network of a common carrier, in general, it is one effective measure that a clock of the digital network clock of the common carrier input from the outside world to the LAN (hereinafter, referred to as "an external clock" for short, when applicable) is divided with its frequency into 8 kHz as the greatest common divisor between 1.544 Mbps of a high speed digital interface and 2.028 Mbps of a PBX private interface, thereby to synchronize with a system clock source of the LAN through a phase-locked loop (hereinafter, referred to as "PLL" for short, when applicable) and is transmitted as a clock in which a high frequency jitter (a swinging of a clock edge) of the external clock is removed to the associated nodes.
FIG. 1 is a block diagram showing an example of a configuration of the above-mentioned well known PLL which includes a phase comparator 21, a low-pass filter (hereinafter, referred as LPF" for short, when applicable), a voltage controlled oscillator (hereinafter, referred to as "VCO" for short, when applicable), and a dividing circuit 24.
The PLL shown in FIG. 1 operates in such a way that the phase comparator 21 compares the phase of a clock (external clock) 26 from a circuitry network provided outside the system (external network) and that of an output clock of the dividing circuit 24 (hereinafter, referred to as "a PLL output clock", when applicable) with each other, LPF 22 converts a phase comparison output 27 of the phase comparator 21 into a smoothed voltage signal 28, and VCO 23 is controlled by an output of LPF so as to oscillate a signal with a predetermined frequency.
VCO 23 is an oscillator of the voltage controlled type wherein its oscillation frequency is varied in accordance with the voltage of the output 28 of LPF. The frequency of an output 29 of VCO is divided into 1/N (N: integral number equal to or larger than 2) by the dividing circuit 24. Then, when the external clock is in a normal state, the resultant clock 25 is utilized as the system clock source of the LAN.
In a PLL having such a configuration, if the frequency of the output of VCO 23 is varied due to some unavoidable causes, the frequency of the output clock 25 of PLL will also be varied. On the basis of the frequency variation, the phase comparator 21 outputs its output signal 27 to LPF 22 so as to decrease the phase difference. As a result, the difference in phase between the clock 26 of the external network and the PLL output clock 25 is gradually decreased so that both the clocks can synchronize with each other. Incidentally, normally, the frequency of the output 29 of VCO is set to N times as large as that of the synchronous clock of the external network and thus the clock thereof is supplied as the system clock of the system (apparatus) accommodated in each node in the LAN.
In addition, if the phase variation (step) occurs in the external clock 26 (an input clock of the PLL), the output 27 of the phase comparator 21 corresponding to that phase variation is converted into the voltage signal 28 by LPF 22 so that the frequency of the output 29 of VCO is varied. This frequency variation of the output 29 of VCO is increased or decreased so as to decrease the difference in phase between the external clock 26 and the output clock 25 of the PLL, i.e., to decrease the output 27 of the phase comparator 21, and when it has been finally completed that the phase of the PLL output clock 25 follows the phase of the external clock 26, the frequency of the output 29 of VCO becomes a fixed frequency. More specifically, if the phase variation occurs in the external clock, the frequency of the output 29 of the VCO is varied, whereby the temporal frequency variation is caused in the PLL output clock 25.
By the temporal frequency variation of PLL, there arises a problem that a fault such as mistaken sampling of the data may occur in the system (apparatus) accommodated in each node in LAN in some cases, and as a result, temporary communication cannot be performed. Since this fault is a fault relating to the system clock, the influence of the fault becomes large as the scale of the LAN is larger. In addition, in the system requiring the real time processing, the communication impossible period of time due to that fault reduces the performance of the system.
As the means of solving the above-mentioned problem, there is known a method wherein an elastic buffer is used and the data is temporarily stored in the elastic buffer, whereby the temporal frequency variation of PLL is absorbed. An example of utilizing this method is shown in FIG. 2. In FIG. 2, the reference numeral 30 designates an elastic buffer; the reference numeral 31 designates the PLL; the reference numeral 32 designates an external system (apparatus); the reference numeral 33 designates an internal system (apparatus); the reference numeral 34 designates write data; the reference numeral 35, a write clock; the reference numeral 36, read data; and the reference numeral 37, a read clock.
The write data 34 which has been received from the external system (apparatus) is input to the elastic buffer 30 using the write clock 35. On the other hand, the data which has been fetched from the elastic buffer 30 using the read clock 37 by the internal system (apparatus) is the read data 36. As long as the clock of the external system (apparatus) synchronizes with the clock of the internal system (apparatus), the average speed of the reading operation is the same as that of the writing operation. Even if a temporal frequency variation of the PLL 31 occurs, the capacity of the data in the elastic buffer 30 is increased or decreased, whereby the temporal frequency variation is absorbed and thus the internal system (apparatus) can receive the data without hindrance. In addition, in the case where the temporal frequency variation is large, the capacity of the elastic buffer 30 itself is increased, whereby it is possible to prevent the internal system from being influenced by the faults of the overflow and the underflow (deficiency of data) of the elastic buffer. The configuration of the circuit of FIG. 2 is shown in JP-A-1-264426 for example.